The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2024

Filed:

Apr. 14, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chih-Horng Chang, Taipei, TW;

Tin-Hao Kuo, Hsinchu, TW;

Chen-Shien Chen, Zhubei, TW;

Yen-Liang Lin, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/13 (2013.01); H01L 24/11 (2013.01); H01L 24/14 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 25/50 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05552 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/05599 (2013.01); H01L 2224/10145 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/13011 (2013.01); H01L 2224/13012 (2013.01); H01L 2224/13015 (2013.01); H01L 2224/13018 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13083 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/14051 (2013.01); H01L 2224/1412 (2013.01); H01L 2224/14152 (2013.01); H01L 2224/14153 (2013.01); H01L 2224/16056 (2013.01); H01L 2224/16059 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81345 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/2064 (2013.01); H01L 2924/384 (2013.01); Y10T 428/12493 (2015.01); Y10T 428/24479 (2015.01);
Abstract

The present disclosure relates to an integrated chip structure having a first substrate including a plurality of transistor devices disposed within a semiconductor material. An interposer substrate includes vias extending through a silicon layer. A copper bump is disposed between the first substrate and the interposer substrate. The copper bump has a sidewall defining a recess. Solder is disposed over the copper bump and continuously extending from over the copper bump to within the recess. A conductive layer is disposed between the first substrate and the interposer substrate and is separated from the copper bump by the solder.


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