The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2024

Filed:

Jun. 22, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Adel Elsherbini, Tempe, AZ (US);

Feras Eid, Chandler, AZ (US);

Georgios Dogiamis, Chandler, AZ (US);

Beomseok Choi, Chandler, AZ (US);

Henning Braunisch, Phoenix, AZ (US);

William Lambert, Tempe, AZ (US);

Krishna Bharath, Chandler, AZ (US);

Johanna Swan, Scottsdale, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/48 (2006.01); H01L 23/50 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H01L 23/50 (2013.01); H01L 21/4853 (2013.01); H01L 21/563 (2013.01); H01L 23/3185 (2013.01); H01L 23/367 (2013.01); H01L 23/481 (2013.01); H01L 23/562 (2013.01); H01L 24/16 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H05K 1/181 (2013.01); H01L 2224/16227 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01); H01L 2924/18161 (2013.01);
Abstract

An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.


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