The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2024

Filed:

Jan. 18, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Cheng-Wei Chang, Taipei, TW;

Min-Hsiu Hung, Tainan, TW;

Hung-Yi Huang, Hsinchu, TW;

Chun Chieh Wang, Kaohsiung, TW;

Yu-Ting Lin, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 23/532 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02274 (2013.01); H01L 21/28518 (2013.01); H01L 21/762 (2013.01); H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 21/76889 (2013.01); H01L 21/823864 (2013.01); H01L 23/53266 (2013.01); H01L 21/823418 (2013.01);
Abstract

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.


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