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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12080761 B1

PDFFull Text
Date of Patent:
Sep. 03, 2024

Filed:

Jan. 24, 2022

Fully strained channel

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shahaji B. More, Zhubei, TW;

Huai-Tei Yang, Hsin-Chu, TW;

Zheng-Yang Pan, Zhubei, TW;

Shih-Chieh Chang, Taipei, TW;

Chun-Chieh Wang, Kaohsiung, TW;

Cheng-Han Lee, New Taipei, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Attorney:

Sterne, Kessler, Goldstein & Fox P.L.L.C.

Primary Examiner:

Julia Slutsker

Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/74 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1054 (2013.01); H01L 21/02057 (2013.01); H01L 21/02645 (2013.01); H01L 21/3065 (2013.01); H01L 21/308 (2013.01); H01L 21/74 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 21/823892 (2013.01); H01L 27/0924 (2013.01); H01L 27/0928 (2013.01); H01L 29/0653 (2013.01); H01L 29/1083 (2013.01); H01L 29/66795 (2013.01); H01L 29/78 (2013.01); H01L 29/7842 (2013.01); H01L 29/7851 (2013.01); H01L 21/02532 (2013.01); H01L 21/0262 (2013.01); H01L 21/02639 (2013.01); H01L 21/02661 (2013.01);
Abstract

The present disclosure describes an exemplary fin structure formed on a substrate. The disclosed fin structure comprises an n-type doped region formed on a top portion of the substrate, a silicon epitaxial layer on the n-type doped region, and an epitaxial stack on the silicon epitaxial layer, wherein the epitaxial stack comprises a silicon-based seed layer in physical contact with the silicon epitaxial layer. The fin structure can further comprise a liner surrounding the n-type doped region, and a dielectric surrounding the liner.

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