The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2024

Filed:

Aug. 20, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Guan-Wei Huang, Hsinchu, TW;

Yu-Shan Lu, Zhubei, TW;

Yu-Bey Wu, Hsinchu, TW;

Jiun-Ming Kuo, Taipei, TW;

Yuan-Ching Peng, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0922 (2013.01); H01L 21/0259 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/82385 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/4908 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01);
Abstract

A semiconductor structure that includes a first semiconductor fin and a second semiconductor fin disposed over a substrate and adjacent to each other, a metal gate stack disposed over the substrate, and source/drain features disposed in each of the first semiconductor fin and the second semiconductor fin to engage with the metal gate stack. The metal gate stack includes a first region disposed over the first semiconductor fin, a second region disposed over the second semiconductor fin, and a third region connecting the first region to the second region in a continuous profile, where the first region is defined by a first gate length and the second region is defined by a second gate length less than the first gate length.


Find Patent Forward Citations

Loading…