The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2024

Filed:

Aug. 18, 2023
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Li Fong Chong, Melaka, MY;

Yee Beng Daryl Yeow, Melaka, MY;

Chii Shang Hong, Melaka, MY;

Azlina Kassim, Melaka, MY;

Hui Kin Lit, Melaka, MY;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/433 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4334 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 23/315 (2013.01); H01L 23/49503 (2013.01); H01L 23/562 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48245 (2013.01);
Abstract

A semiconductor device includes a semiconductor package, including a package body that includes an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the encapsulant portion and the isolation structure are each electrically insulating structures, wherein the isolation structure has a greater thermal conductivity than the encapsulant portion, and wherein the isolation structure is thermally coupled to the semiconductor die, and a releasable layer affixed to the semiconductor package, wherein a first outer face of the package body includes a first surface of the isolation structure, wherein the releasable layer at least partially covers the first surface of the isolation structure, and wherein the releasable layer is releasable from the semiconductor package.


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