The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2024

Filed:

Jun. 17, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Joung-Wei Liou, Hsinchu, TW;

Yu Lun Ke, Hsinchu, TW;

Yi-Wei Chiu, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02164 (2013.01); H01L 21/02205 (2013.01); H01L 21/02211 (2013.01); H01L 21/0228 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01);
Abstract

Methods to form low-k dielectric materials for use as intermetal dielectrics in multilevel interconnect systems, along with their chemical and physical properties, are provided. The deposition techniques described include PECVD, PEALD, and ALD processes where the precursors such as TEOS and MDEOS may provide the requisite O-atoms and Ogas may not be used as one of the reactants. The deposition techniques described further include PECVD, PEALD, and ALD processes where Ogas may be used and, along with the Ogas, precursors containing embedded Si—O—Si bonds, such as (CHO)—Si—O—Si—(CHO)) and (CH)—Si—O—Si—(CH)may be used.


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