The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2024

Filed:

Jul. 28, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Kuan-Jung Chen, Hsin-Chu, TW;

Tsung-Lin Lee, New Taipei, TW;

Chung-Ming Lin, Taichung, TW;

Wen-Chih Chiang, Hsin-Chu, TW;

Cheng-Hung Wang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/74 (2006.01); H01L 23/535 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/743 (2013.01); H01L 23/535 (2013.01);
Abstract

Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.


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