The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2024

Filed:

Dec. 06, 2019
Applicant:

Weifang Goertek Microelectronics Co., Ltd., Shandong, CN;

Inventors:

Haisheng Wang, Shandong, CN;

Dewen Tian, Shandong, CN;

Qinglin Song, Shandong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 21/306 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/561 (2013.01); H01L 21/30604 (2013.01); H01L 23/552 (2013.01); H01L 24/16 (2013.01); H01L 2224/16225 (2013.01);
Abstract

Disclosed is a packaging method for circuit units, wherein the circuit units comprise a silicon layer substrate and a silicon dioxide layer overlaid on the silicon layer substrate. The packaging method for a circuit unit comprises: attaching a plurality of circuit units to a circuit baseplate in a spaced and inverted mode, wherein the silicon dioxide layer is attached to the circuit baseplate, and the silicon layer substrate faces away from the circuit baseplate; forming an insulator between the circuit units; removing the silicon layer substrate to expose the silicon dioxide layer; and forming an electromagnetic shielding layer on the silicon dioxide layer and the insulator.


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