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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12068250 B1

PDFFull Text
Date of Patent:
Aug. 20, 2024

Filed:

Apr. 20, 2022

3d nand memory device and method of forming the same

Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventors:

Zhongwang Sun, Wuhan, CN;

Zhong Zhang, Wuhan, CN;

Wenxi Zhou, Wuhan, CN;

Zhiliang Xia, Wuhan, CN;

Assignee:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Farun Lu

Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/535 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 21/311 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 21/76895 (2013.01); H01L 23/5226 (2013.01); H01L 23/535 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02); H10B 43/50 (2023.02);
Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, a stack of word line layers and insulating layers that are stacked alternatingly over the substrate, and channel structures formed in a first array region and a second array region of the stack. The first array region and the second array region are positioned at opposing sides of the stack. A first staircase is formed in a connection region of the stack over the substrate, where the connection region is arranged between the first and second array regions. A second staircase is formed in the connection region of the stack over the substrate, and the connection region in the stack includes a separation region between the first and second staircases.

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