The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2024

Filed:

Jul. 22, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Li-Hsien Huang, Hsinchu County, TW;

An-Jhih Su, Taoyuan, TW;

Der-Chyang Yeh, Hsin-Chu, TW;

Hua-Wei Tseng, New Taipei, TW;

Chiang Lin, Taoyuan, TW;

Ming-Shih Yeh, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49822 (2013.01); H01L 21/4857 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 25/105 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01);
Abstract

A method of manufacturing a semiconductor package includes forming an encapsulated semiconductor device and forming a redistribution structure over the encapsulated semiconductor device, where the encapsulated semiconductor device includes a semiconductor device encapsulated by an encapsulating material. Forming the redistribution structure includes forming a first dielectric layer on the encapsulated semiconductor device, and forming a first redistribution circuit layer on the first dielectric layer by a plating process carried out at a current density of substantially 4˜6 amperes per square decimeter, where the first dielectric layer comprises a first via opening. An upper surface of the first redistribution circuit layer filling the first via opening is substantially coplanar with an upper surface of the rest of the first redistribution circuit layer.


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