The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2024

Filed:

Nov. 23, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Han-Yu Lin, Hsinchu, TW;

Szu-Hua Chen, Hsinchu, TW;

Kuan-Kan Hu, Hsinchu, TW;

Kenichi Sano, Hsinchu, TW;

Po-Cheng Wang, Kaohsiung, TW;

Wei-Yen Woon, Hsinchu, TW;

Pinyen Lin, Rochester, NY (US);

Che Chi Shih, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823431 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/6675 (2013.01); H01L 29/78618 (2013.01); H01L 29/78672 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01);
Abstract

The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.


Find Patent Forward Citations

Loading…