The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2024

Filed:

May. 21, 2023
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Liang Yi, Singapore, SG;

Zhiguo Li, Singapore, SG;

Xiaojuan Gao, Singapore, SG;

Chi Ren, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42328 (2013.01); H01L 29/40114 (2019.08); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01);
Abstract

A method for forming a semiconductor memory device is disclosed. A substrate is provided. A source diffusion region is formed in the substrate. Two floating gates are on opposite sides of the source diffusion region. A first dielectric cap layer is formed directly on each of the floating gates. An erase gate is formed on the source diffusion region. The erase gate partially overlaps an upper inner corner of each of the floating gates. A second dielectric cap layer is formed on the erase gate and the first dielectric cap layer. A select gate is formed on a sidewall of the first dielectric cap layer in a self-aligned manner. A drain diffusion region is formed in the substrate and adjacent to the select gate.


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