The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 06, 2024
Filed:
Aug. 31, 2021
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Zhiru Yu, San Jose, CA (US);
Yan Feng, Hsinchu, TW;
Lin Zhang, Hsinchu, TW;
Danping Peng, Fremont, CA (US);
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
In a method of manufacturing a lithographic mask of an integrated circuit for semiconductor device manufacturing an optical proximity correction (OPC) process to a layout pattern of the integrated circuit is performed to produce a corrected layout pattern. An inverse lithographic technology (ILT) process to the corrected layout pattern is also performed to enhance the corrected layout pattern to produce an OPC-ILT-enhanced layout pattern of the lithographic mask. A first contour image associated with the OPC-ILT-enhanced layout pattern is generated when the OPC-ILT-enhanced layout pattern of the lithographic mask is projected on a wafer. The features of the generated first contour image are extracted. And a second contour image of a developed photo resist pattern on the wafer associated with the OPC-ILT-enhanced layout pattern as an output of a deep neural network is generated.