The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2024

Filed:

Aug. 10, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chen-Hao Huang, Hsinchu, TW;

Hau-Yan Lu, Hsinchu, TW;

Sui-Ying Hsu, Hsinchu, TW;

Yuehying Lee, Hsinchu, TW;

Chien-Ying Wu, Hsinchu, TW;

Chien-Chang Lee, Hsinchu, TW;

Chia-Ping Lai, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/34 (2006.01); G02B 6/30 (2006.01); G02B 6/42 (2006.01);
U.S. Cl.
CPC ...
G02B 6/34 (2013.01); G02B 6/30 (2013.01); G02B 6/4204 (2013.01);
Abstract

A method of making a chip includes depositing a first polysilicon layer on a top surface and a bottom surface of a substrate. The method further includes patterning the first polysilicon layer to define a recess, wherein the first polysilicon layer is completed removed from the recess. The method further includes implanting dopants into the substrate to define an implant region. The method further includes depositing a contact etch stop layer (CESL) in the recess, wherein the CESL covers the implant region. The method further includes patterning the CESL to define a CESL block. The method further includes forming a waveguide and a grating in the substrate. The method further includes forming an interconnect structure over the waveguide, the grating and the CESL block. The method further includes etching the interconnect structure to define a cavity aligned with the grating.


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