The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2024
Filed:
Jun. 27, 2023
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Andrew Collins, Chandler, AZ (US);
Sujit Sharan, Chandler, AZ (US);
Jianyong Xie, Chandler, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/66 (2006.01); H01L 21/48 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/16 (2023.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/66 (2013.01); H01L 21/4846 (2013.01); H01L 23/5223 (2013.01); H01L 23/5286 (2013.01); H01L 23/5381 (2013.01); H01L 23/5389 (2013.01); H01L 25/16 (2013.01); H01L 25/50 (2013.01); H01L 23/481 (2013.01); H01L 2223/6666 (2013.01); H01L 2223/6672 (2013.01);
Abstract
A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.