The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

Apr. 03, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Huan-Chieh Su, Changhua County, TW;

Chun-Yuan Chen, Hsinchu, TW;

Lo-Heng Chang, Hsinchu, TW;

Li-Zhen Yu, New Taipei, TW;

Cheng-Chi Chuang, New Taipei, TW;

Chih-Hao Wang, Hsinchu County, TW;

Kuan-Lun Cheng, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823481 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/7855 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01); H01L 21/823437 (2013.01);
Abstract

Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes channel members over a backside dielectric feature, a gate structure wrapping around the channel members, an epitaxial feature abutting the channel members, a first isolation feature disposed on a first sidewall of the gate structure and extending through the backside dielectric feature, and a second isolation feature disposed on a second sidewall of the gate structure and extending through the backside dielectric feature. A top surface of the first isolation feature is above a top surface of the second isolation feature.


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