The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2024
Filed:
Feb. 16, 2021
Globalwafers Japan Co., Ltd., Niigata, JP;
Takeshi Senda, Niigata, JP;
Shingo Narimatsu, Niigata, JP;
GLOBALWAFERS JAPAN CO., LTD., Niigata, JP;
Abstract
A semiconductor silicon wafer manufacturing method is provided, where P aggregate defects and SF in an epitaxial layer can be suppressed. A silicon wafer substrate cut from a monocrystal ingot is doped with phosphorus and has a resistivity of 1.05 mΩ·cm or less and a concentration of solid-solution oxygen of 0.9×10atoms/cm. The method includes steps of mirror-polishing substrates and heat treatment, where after the mirror-polishing step, the substrate is kept at a temperature from 700° C. to 850° for 30 to 120 minutes, then after the temperature rise, kept at a temperature from 1100° C. to 1250° for 30 to 120 minutes, and after cooling, kept at a temperature from 700° C. to 450° C. for less than 10 minutes as an experience time. The heat treatment step is performed in a mixture gas of hydrogen and argon. The method includes an epitaxial layer deposition step to a thickness of 1.3 μm to 10.0 μm.