The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2024

Filed:

Apr. 01, 2021
Applicant:

Zhuhai Access Semiconductor Co., Ltd, Guangdong, CN;

Inventors:

Xianming Chen, Guangdong, CN;

Lei Feng, Guangdong, CN;

Benxia Huang, Guangdong, CN;

Jindong Feng, Guangdong, CN;

Yejie Hong, Guangdong, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01P 11/00 (2006.01); B32B 37/00 (2006.01); C25D 5/00 (2006.01); C25D 7/00 (2006.01); B32B 37/12 (2006.01); C25D 5/02 (2006.01);
U.S. Cl.
CPC ...
H01P 11/008 (2013.01); B32B 37/1284 (2013.01); C25D 5/022 (2013.01); C25D 7/00 (2013.01);
Abstract

A method for manufacturing an embedded package structure having an air resonant cavity according to an embodiment includes manufacturing a first substrate including a first insulating layer, a chip embedded in the insulating layer, and a wiring layer on a terminal face of the chip of the first substrate, wherein the wiring layer is provided thereon with an opening revealing the terminal face of the chip; manufacturing a second substrate which comprises a second insulating layer; locally applying a first adhesive layer on the wiring layer such that the opening revealing the terminal face of the chip is not covered; and applying a second adhesive layer on the second substrate; and attaching and curing the first adhesive layer of the first substrate and the second adhesive layer of the second substrate to obtain an embedded package structure having an air resonant cavity on the terminal face of the chip.


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