The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2024

Filed:

Jul. 12, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Aaron D. Lilak, Beaverton, OR (US);

Christopher J. Jezewski, Portland, OR (US);

Willy Rachmady, Beaverton, OR (US);

Rishabh Mehandru, Portland, OR (US);

Gilbert Dewey, Beaverton, OR (US);

Anh Phan, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823431 (2013.01); H01L 29/7842 (2013.01); H01L 29/7845 (2013.01); H01L 29/7846 (2013.01); H01L 29/785 (2013.01);
Abstract

In an embodiment of the present disclosure, a device structure includes a fin structure, a gate on the fin structure, and a source and a drain on the fin structure, where the gate is between the source and the drain. The device structure further includes an insulator layer having a first insulator layer portion adjacent to a sidewall of the source, a second insulator layer portion adjacent to a sidewall of the drain, and a third insulator layer portion therebetween adjacent to a sidewall of the gate, and two or more stressor materials adjacent to the insulator layer. The stressor materials can be tensile or compressively stressed and may strain a channel under the gate.


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