The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2024

Filed:

Jul. 13, 2023
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Oleg Golonzka, Beaverton, OR (US);

Swaminathan Sivakumar, Beaverton, OR (US);

Charles H. Wallace, Portland, OR (US);

Tahir Ghani, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/28 (2006.01); H01L 21/306 (2006.01); H01L 21/32 (2006.01); H01L 21/8234 (2006.01); H01L 23/535 (2006.01); H01L 27/02 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/28008 (2013.01); H01L 21/30625 (2013.01); H01L 21/76805 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823468 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 23/535 (2013.01); H01L 27/0207 (2013.01); H01L 27/088 (2013.01); H01L 27/0886 (2013.01); H01L 29/0653 (2013.01); H01L 29/66545 (2013.01); H01L 21/32 (2013.01);
Abstract

Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.


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