The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2024

Filed:

Nov. 21, 2022
Applicants:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

National Taiwan University, Taipei, TW;

National Taiwan Normal University, Taipei, TW;

Inventors:

Chun-Yi Chou, Hsinchu, TW;

Po-Hsien Cheng, Taipei, TW;

Tse-An Chen, Taoyuan, TW;

Miin-Jang Chen, Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); C23C 16/04 (2006.01); H01L 21/28 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 23/522 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0228 (2013.01); C23C 16/042 (2013.01); H01L 21/02164 (2013.01); H01L 21/02274 (2013.01); H01L 21/28194 (2013.01); H01L 21/76224 (2013.01); H01L 21/76829 (2013.01); H01L 21/76877 (2013.01); H01L 21/823821 (2013.01); H01L 21/823857 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 23/5226 (2013.01); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 29/401 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract

A device includes a conductive feature, a first dielectric layer, a via, an etch stop layer, a second dielectric layer, and a conductive line. The first dielectric layer is above the conductive feature. The via is in the first dielectric layer and above the conductive feature. The etch stop layer is above the first dielectric layer. A side surface of the etch stop layer is coterminous with a sidewall of the via. The second dielectric layer is above the etch stop layer. The conductive line is in the second dielectric layer and over the via. The conductive line is in contact with the side surface of the etch stop layer and a top surface of the etch stop layer.


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