The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2024

Filed:

Sep. 21, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jeremy D. Ecton, Gilbert, AZ (US);

Aleksandar Aleksov, Chandler, AZ (US);

Brandon C. Marin, Chandler, AZ (US);

Yonggang Li, Chandler, AZ (US);

Leonel Arana, Phoenix, AZ (US);

Suddhasattwa Nad, Chandler, AZ (US);

Haobo Chen, Chandler, AZ (US);

Tarek Ibrahim, Mesa, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/768 (2006.01); H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 21/76838 (2013.01); H01L 23/5385 (2013.01); H05K 1/11 (2013.01);
Abstract

Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.


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