The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2024

Filed:

Dec. 23, 2020
Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventors:

Hang Yin, Wuhan, CN;

Zhipeng Wu, Wuhan, CN;

Kai Han, Wuhan, CN;

Lu Zhang, Wuhan, CN;

Pan Wang, Wuhan, CN;

Xiangning Wang, Wuhan, CN;

Hui Zhang, Wuhan, CN;

Jingjing Geng, Wuhan, CN;

Meng Xiao, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H01L 29/42352 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/42328 (2013.01); H01L 29/42336 (2013.01); H01L 29/42344 (2013.01); H01L 29/66545 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7889 (2013.01); H01L 29/7926 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02);
Abstract

Aspects of the disclosure provide a method for fabricating a semiconductor device having an first stack of alternating insulating layers and sacrificial word line layers arranged over a substrate, the first stack including a core region and a staircase region. The method can include forming a first dielectric trench in the core region of the first stack, forming a second dielectric trench that is adjacent to and connected with the first dielectric trench in the staircase region of the first stack, and forming dummy channel structures extending through the first stack where the dummy channel structures are spaced apart from the second dielectric trench.


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