The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2024

Filed:

Jan. 20, 2022
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Jeffrey Smith, Clifton Park, NY (US);

Kandabara Tapily, Mechanicville, NY (US);

Lars Liebmann, Mechanicville, NY (US);

Daniel Chanemougame, Niskayuna, NY (US);

Mark Gardner, Cedar Creek, TX (US);

H. Jim Fulford, Marianna, FL (US);

Anton J. Devilliers, Clifton Park, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823842 (2013.01); H01L 21/823821 (2013.01); H01L 21/823857 (2013.01); H01L 27/0922 (2013.01); H01L 27/0924 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method for microfabrication of a three dimensional transistor stack having gate-all-around field-effect transistor devices. The channels hang between source/drain regions. Each channel is selectively deposited with layers of materials designed for adjusting the threshold voltage of the channel. The layers may be oxides, high-k materials, work function materials and metallization. The three dimensional transistor stack forms an array of high threshold voltage devices and low threshold voltage devices in a single package.


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