The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2024

Filed:

Jun. 16, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ping-Wei Wang, Hsinchu, TW;

Lien Jung Hung, Taipei, TW;

Kuo-Hsiu Hsu, Zhongli, TW;

Kian-Long Lim, Hsinchu, TW;

Yu-Kuan Lin, Taipei, TW;

Chia-Hao Pao, Kaohsiung, TW;

Chih-Chuan Yang, Tainan, TW;

Shih-Hao Lin, Hsinchu, TW;

Choh Fei Yeap, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); G11C 11/412 (2006.01); G11C 11/419 (2006.01); H01L 21/66 (2006.01); H04N 21/426 (2011.01); H10B 10/00 (2023.01); H10B 41/35 (2023.01);
U.S. Cl.
CPC ...
H10B 10/12 (2023.02); G11C 11/412 (2013.01); G11C 11/419 (2013.01); H01L 22/12 (2013.01); H01L 23/528 (2013.01); H04N 21/42692 (2013.01); H10B 10/00 (2023.02); H10B 41/35 (2023.02); G11C 2213/74 (2013.01); G11C 2213/79 (2013.01); H01L 2924/1437 (2013.01);
Abstract

A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells includes a substrate having a front side and a back side with a transistor of the memory cell being formed on the front side and the back side being opposite of the front side, a first interconnect layer on the front side to provide a bit line of the memory cell, a second interconnect layer on the front side to provide a word line of the memory cell, a third interconnect layer on the back side to provide a supply voltage to the memory cell and a fourth interconnect layer on the back side to provide a ground voltage to the memory cell, widths of the bit line and the word line being chosen to reduce current-resistance drop.


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