The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2024

Filed:

Mar. 15, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Wen-Chuan Tai, Hsinchu, TW;

Fan Hu, Taipei, TW;

Hsiang-Fu Chen, Hsinchu County, TW;

Li-Chun Peng, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/50 (2006.01); H01L 23/10 (2006.01);
U.S. Cl.
CPC ...
H01L 24/08 (2013.01); H01L 21/50 (2013.01); H01L 23/10 (2013.01); H01L 24/09 (2013.01); H01L 24/80 (2013.01); H01L 2224/0801 (2013.01); H01L 2224/08053 (2013.01); H01L 2224/08059 (2013.01); H01L 2224/08221 (2013.01); H01L 2224/0903 (2013.01); H01L 2224/09055 (2013.01); H01L 2224/80203 (2013.01); H01L 2224/80805 (2013.01); H01L 2224/8083 (2013.01); H01L 2224/80895 (2013.01); H01L 2924/1611 (2013.01); H01L 2924/1616 (2013.01); H01L 2924/16235 (2013.01); H01L 2924/1631 (2013.01); H01L 2924/16315 (2013.01); H01L 2924/1632 (2013.01);
Abstract

A bonding method and a bonding structure are provided. A device substrate is provided including a plurality of semiconductor devices, wherein each of the semiconductor devices includes a first bonding layer. A cap substrate is provided including a plurality of cap structures, wherein each of the cap structures includes a second bonding layer, the second bonding layer having a planar surface and a first protrusion protruding from the planar surface. The device substrate is bonded to the cap substrate by engaging the first protrusion of the second bonding layer of each of the cap structures with the corresponding first bonding layer of each of the semiconductor devices in the device substrate.


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