The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2024

Filed:

Jun. 14, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Shao-Ming Koh, Hsinchu, TW;

Chen-Ming Lee, Taoyuan County, TW;

Fu-Kai Yang, Hsinchu, TW;

Mei-Yun Wang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/302 (2006.01); H01L 21/306 (2006.01); H01L 21/3065 (2006.01); H01L 21/311 (2006.01); H01L 21/4757 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 23/485 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/02057 (2013.01); H01L 21/28525 (2013.01); H01L 21/302 (2013.01); H01L 21/30608 (2013.01); H01L 21/3065 (2013.01); H01L 21/31138 (2013.01); H01L 21/47573 (2013.01); H01L 21/76801 (2013.01); H01L 21/823418 (2013.01); H01L 21/823437 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 23/485 (2013.01); H01L 27/0924 (2013.01); H01L 29/7848 (2013.01); H01L 29/165 (2013.01); H01L 29/41791 (2013.01); H01L 29/665 (2013.01);
Abstract

Semiconductor devices and methods of forming the same are provided. In one embodiments, a semiconductor device includes an n-type transistor region and a p-type transistor region. The n-type transistor region includes a first gate stack, a first gate spacer over sidewalls of the first gate stack, an n-type epitaxial feature in a source/drain (S/D) region of the n-type transistor region, and a first metal silicide layer over the n-type epitaxial feature. The p-type transistor region includes a second gate stack, a second gate spacer over sidewalls of the second gate stack, a p-type epitaxial feature in an S/D region of the p-type transistor region, a dopant-containing implant layer over the p-type epitaxial feature, and a second metal silicide layer over the dopant-containing implant layer. The dopant-containing implant layer includes a metallic dopant.


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