The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2024

Filed:

Sep. 03, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Ka Fai Chang, Hsinchu, TW;

Fong-Yuan Chang, Hsinchu County, TW;

Chin-Chou Liu, Hsinchu County, TW;

Yi-Kan Cheng, Taipei, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/822 (2006.01); G06F 30/398 (2020.01); G06F 119/06 (2020.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8221 (2013.01); G06F 30/398 (2020.01); H01L 23/5227 (2013.01); H01L 23/5286 (2013.01); H01L 24/42 (2013.01); G06F 2119/06 (2020.01);
Abstract

A method for forming an integrated circuit (IC) is provided. The method includes the following operations. A circuit layout including a first load region and a second load region is received. A full power network of the circuit layout is obtained. The full power network is transformed into a first power network according to the first load region. A first power simulation is performed upon the first power network. The full power network is transformed into a second power network according to the second load region. A second power simulation is performed upon the second power network. The IC is fabricated according to the circuit layout.


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