The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2024
Filed:
Dec. 05, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Jui Fu Hsieh, Zhubei, TW;
Chih-Teng Liao, Hsinchu, TW;
Chih-Shan Chen, New Taipei, TW;
Yi-Jen Chen, Hsinchu, TW;
Tzu-Chan Weng, Kaohsiung, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed by a plasma etching process. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, the plasma process comprises applying pulsed bias voltage and RF voltage with pulsed power.