The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2024

Filed:

Dec. 16, 2022
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Jun Liu, Wuhan, CN;

Weihua Cheng, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/78 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06524 (2013.01);
Abstract

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, first semiconductor structures are formed. At least one of the first semiconductor structures includes a processor, static random-access memory (SRAM) cells, and a first bonding layer comprising first bonding contacts. Second semiconductor structures are formed. At least one of the second semiconductor structures comprises dynamic random-access memory (DRAM) cells and a second bonding layer comprising second bonding contacts. The first semiconductor structures and the second semiconductor structures are bonded. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure. At least one of the first semiconductor structures and the second semiconductor structures further includes a peripheral circuit.


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