Capacitor array, method for manufacturing the same and memory

Abstract

The present disclosure provides a method for manufacturing capacitor array, including: forming, on an upper surface of the substrate, a laminated structure including sacrificial layers and support layers; forming a patterned mask layer on an upper surface of the laminated structure; etching the laminated structure based on the patterned mask layer to form a through hole, wherein after the through hole is formed, the patterned mask layer is retained on the upper surface of the laminated structure, and the through hole penetrates through the patterned mask layer and the laminated structure; forming a first electrode on a sidewall and at a bottom of the through hole; forming, in the patterned mask layer and the laminated structure, and removing the sacrificial layer based on the opening; forming a capacitor dielectric layer on a surface of the first electrode; and forming a second electrode on a surface of the capacitor dielectric layer.