The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2024

Filed:

Mar. 05, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

U-Ting Chiu, Hsinchu, TW;

Po-Nan Yeh, Hsinchu, TW;

Yu-Shih Wang, Tainan, TW;

Chun-Neng Lin, Hsinchu County, TW;

Ming-Hsi Yeh, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76831 (2013.01); H01L 21/76805 (2013.01); H01L 21/76846 (2013.01); H01L 21/76849 (2013.01); H01L 21/76877 (2013.01); H01L 21/76895 (2013.01); H01L 23/5226 (2013.01); H01L 23/53257 (2013.01); H01L 23/535 (2013.01);
Abstract

A method of forming a semiconductor device includes: forming a semiconductor feature over a substrate, the semiconductor feature includes a conductive region; forming a dielectric layer over the semiconductor feature; patterning the dielectric layer to form a contact opening exposing a top surface of the conductive region; forming a monolayer over the dielectric layer, the top surface of the conductive region remaining exposed; and depositing a conductive material in the contact opening.


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