The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2024

Filed:

Jul. 26, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Shich-Chang Suen, Hsinchu, TW;

Li-Chieh Wu, Hsinchu, TW;

Chi-Jen Liu, Taipei, TW;

He Hui Peng, Changhua, TW;

Liang-Guang Chen, Hsinchu, TW;

Yung-Chung Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 21/288 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02068 (2013.01); H01L 21/02063 (2013.01); H01L 21/0234 (2013.01); H01L 21/28079 (2013.01); H01L 21/28132 (2013.01); H01L 21/288 (2013.01); H01L 21/31105 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/76804 (2013.01); H01L 21/76814 (2013.01); H01L 21/76831 (2013.01); H01L 21/76877 (2013.01); H01L 21/76895 (2013.01); H01L 29/40114 (2019.08); H01L 29/66545 (2013.01);
Abstract

The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a HPOsolution.


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