The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2024

Filed:

Aug. 30, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hsiao-Chien Lin, Tainan, TW;

Hsi Chung Chen, Tainan, TW;

Cheng-Hung Tsai, Kaohsiung, TW;

Chih-Hsuan Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41775 (2013.01); H01L 29/401 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method includes forming a dummy gate structure across a fin, in which the dummy gate structure has a dummy gate dielectric layer and a dummy gate electrode, forming gate spacers on sidewalls of the dummy gate structure, forming source/drain epitaxial structures on sides of the dummy gate structure, performing a first etch process to the dummy gate electrode such that a recessed dummy gate electrode remains over the fin, performing a second etch process to the gate spacers such that recessed gate spacers remain over the sidewalls of the dummy gate structure, removing the recessed dummy gate electrode and the dummy gate dielectric layer after the second etch process to form a recess between the recessed gate spacers, forming a gate structure overfilling the recess, and performing a third etch process to the gate structure such that a recessed gate structure remains between the recessed gate spacers.


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