The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2024

Filed:

Jun. 16, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Cory E. Weber, Hillsboro, OR (US);

Harold W. Kennel, Portland, OR (US);

Willy Rachmady, Beaverton, OR (US);

Gilbert Dewey, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 21/8258 (2006.01); H01L 27/12 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0922 (2013.01); H01L 21/02 (2013.01); H01L 21/8238 (2013.01); H01L 21/823807 (2013.01); H01L 21/8258 (2013.01); H01L 27/0924 (2013.01); H01L 27/1211 (2013.01); H01L 29/045 (2013.01); H01L 29/06 (2013.01); H01L 29/78 (2013.01); H01L 21/02609 (2013.01);
Abstract

Semiconductor nanowire devices having (111)-plane channel sidewalls and methods of fabricating semiconductor nanowire devices having (111)-plane channel sidewalls are described. For example, an integrated circuit structure includes a first semiconductor device including a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising a discrete channel region having <111> lateral sidewalls along a <110> carrier transport direction. The integrated circuit structure also includes a second semiconductor device including a semiconductor fin disposed above the substrate, the semiconductor fin having a channel region with a top and side surfaces, the channel region having <111> lateral sidewalls along a <110> carrier transport direction.


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