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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11985905 B1

PDFFull Text
Date of Patent:
May. 14, 2024

Filed:

Jan. 23, 2023

Highly physical ion resistive spacer to define chemical damage free sub 60nm mram devices

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yi Yang, Fremont, CA (US);

Dongna Shen, San Jose, CA (US);

Yu-Jen Wang, San Jose, CA (US);

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

Haynes and Boone, LLP

Primary Examiner:

Antonio B Crite

Int. Cl.
CPC ...
H10N 50/10 (2023.01); G11C 11/16 (2006.01); H01F 10/32 (2006.01); H01F 41/34 (2006.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01); H01F 41/30 (2006.01);
U.S. Cl.
CPC ...
H10N 50/01 (2023.02); G11C 11/161 (2013.01); H01F 10/3254 (2013.01); H01F 41/34 (2013.01); H10N 50/10 (2023.02); H10N 50/80 (2023.02);
Abstract

A magnetic tunneling junction (MTJ) structure comprises a pinned layer on a bottom electrode. a barrier layer on the pinned layer, wherein a second metal re-deposition layer is on sidewalls of the barrier layer and the pinned layer, a free layer on the barrier layer wherein the free layer has a first width smaller than a second width of the pinned layer, a top electrode on the free layer having a same first width as the free layer wherein a first metal re-deposition layer is on sidewalls of the free layer and top electrode, and dielectric spacers on sidewalls of the free layer and top electrode covering the first metal re-deposition layer wherein the free layer and the top electrode together with the dielectric spacers have a same the second width as the pinned layer wherein the dielectric spacers prevent shorting between the first and second metal re-deposition layers.

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