The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2024

Filed:

Aug. 30, 2021
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Ning Xi, Hefei, CN;

Peimeng Wang, Hefei, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H10B 12/482 (2023.02); H01L 21/0206 (2013.01); H01L 21/76853 (2013.01); H01L 23/528 (2013.01); H10B 12/485 (2023.02);
Abstract

A method for manufacturing a bit line structure includes the following operations. A bit line conductive layer is formed on a surface of a semiconductor substrate, and the bit line conductive layer is partially located in a groove in the surface of the semiconductor substrate. A first protective layer is formed on surfaces of the bit line conductive layer and the semiconductor substrate. A first barrier layer is formed on a surface of the first protective layer. The surface of the first barrier layer is subjected with passivating treatment. A sacrificial layer is formed on the surface of the first barrier layer, and is provided with a filling part filled in the groove. A part, other than the filling part, of the sacrificial layer is cleaned and stripped.


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