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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11984261 B1

PDFFull Text
Date of Patent:
May. 14, 2024

Filed:

Aug. 25, 2021

Integration scheme for breakdown voltage enhancement of a piezoelectric metal-insulator-metal device

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Anderson Lin, Hsinchu, TW;

Chun-Ren Cheng, Hsin-Chu, TW;

Chi-Yuan Shih, Hsinchu, TW;

Shih-Fen Huang, Jhubei, TW;

Yi-Chuan Teng, Zhubei, TW;

Yi Heng Tsai, Hsinchu, TW;

You-Ru Lin, New Taipei, TW;

Yen-Wen Chen, Hsinchu County, TW;

Fu-Chun Huang, Zhubei, TW;

Fan Hu, Taipei, TW;

Ching-Hui Lin, Taichung, TW;

Yan-Jie Liao, Hsinchu, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Attorney:

Eschweiler & Potashnik, LLC

Primary Examiner:

John A Bodnar

Int. Cl.
CPC ...
H01G 4/012 (2006.01); H01G 4/12 (2006.01); H01G 4/228 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 41/047 (2006.01); H01L 41/083 (2006.01); H01L 41/113 (2006.01); H01L 49/02 (2006.01); H10N 30/30 (2023.01); H10N 30/50 (2023.01); H10N 30/87 (2023.01);
U.S. Cl.
CPC ...
H01G 4/012 (2013.01); H01G 4/12 (2013.01); H01G 4/228 (2013.01); H01L 21/31111 (2013.01); H01L 21/32139 (2013.01); H01L 28/60 (2013.01); H10N 30/302 (2023.02); H10N 30/501 (2023.02); H10N 30/508 (2023.02); H10N 30/872 (2023.02);
Abstract

Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.

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