The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2024

Filed:

Dec. 22, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sabareesh Ganapathy, Santa Clara, CA (US);

Fangwen Fu, Folsom, CA (US);

Hong Jiang, El Dorado Hills, CA (US);

James Valerio, North Plains, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 9/54 (2006.01); G06T 1/20 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3838 (2013.01); G06F 9/4881 (2013.01); G06F 9/544 (2013.01); G06T 1/20 (2013.01);
Abstract

Examples described herein relate to a graphics processing unit (GPU) coupled to the memory device, the GPU configured to: execute an instruction thread; determine if a dual directional signal barrier is associated with the instruction thread; and based on clearance of the dual directional signal barrier for a particular signal barrier identifier and a mode of operation, indicate a clearance of the dual directional signal barrier for the mode of operation, wherein the dual directional signal barrier is to provide a single barrier to gate activity of one or more producers based on activity of one or more consumers or gate activity of one or more consumers based on activity of one or more producers.


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