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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11973129 B1

PDFFull Text
Date of Patent:
Apr. 30, 2024

Filed:

Mar. 13, 2023

Semiconductor device structure with inner spacer layer and method for forming the same

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Han-Yu Lin, Nantou County, TW;

Chansyun David Yang, Shinchu, TW;

Fang-Wei Lee, Hsinchu, TW;

Tze-Chung Lin, Hsinchu, TW;

Li-Te Lin, Hsinchu, TW;

Pinyen Lin, Rochester, NY (US);

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

Birch, Stewart, Kolasch & Birch, LLP

Primary Examiner:

Mounir S Amer

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/165 (2006.01); H01L 29/423 (2006.01); H01L 29/775 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6681 (2013.01); H01L 21/0214 (2013.01); H01L 21/02167 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/31116 (2013.01); H01L 21/32105 (2013.01); H01L 21/3211 (2013.01); H01L 21/7682 (2013.01); H01L 21/76837 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823468 (2013.01); H01L 29/0673 (2013.01); H01L 29/165 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/775 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method for forming a semiconductor device structure is provided. The semiconductor device includes forming nanowire structures stacked over a substrate and spaced apart from one another, and forming a dielectric material surrounding the nanowire structures. The dielectric material has a first nitrogen concentration. The method also includes treating the dielectric material to form a treated portion. The treated portion of the dielectric material has a second nitrogen concentration that is greater than the first nitrogen concentration. The method also includes removing the treating portion of the dielectric material, thereby remaining an untreated portion of the dielectric material as inner spacer layers; and forming the gate stack surrounding nanowire structures and between the inner spacer layers.

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