The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2024
Filed:
Feb. 25, 2022
Adeia Semiconductor Bonding Technologies Inc., San Jose, CA (US);
Guilian Gao, San Jose, CA (US);
Javier A. DeLaCruz, San Jose, CA (US);
Shaowu Huang, Sunnyvale, CA (US);
Liang Wang, Newark, CA (US);
Gaius Gillman Fountain, Jr., Youngsville, NC (US);
Rajesh Katkar, Milpitas, CA (US);
Cyprian Emeka Uzoh, San Jose, CA (US);
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC., San Jose, CA (US);
Abstract
Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.