The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2024
Filed:
Aug. 09, 2021
Applicants:
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;
Jium-ming Lin, Hsinchu, TW;
Inventors:
Assignees:
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;
Other;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/552 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01); H01Q 1/22 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5383 (2013.01); H01L 21/4857 (2013.01); H01L 23/552 (2013.01); H01L 24/16 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01Q 1/22 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/73103 (2013.01); H01L 2224/9211 (2013.01);
Abstract
A wafer stack structure includes an interlayer, a first wafer, and a second wafer. The interlayer has a first surface and a second surface opposite to the first surface. The intermediate layer includes a dielectric material layer and a redistribution layer embedded in the dielectric material layer. The first wafer is disposed on the first surface of the interlayer. The second wafer is disposed on the second surface of the interlayer. The second wafer is electrically connected to the first wafer through the redistribution layer of the interlayer.