logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11967558 B1

PDFFull Text
Date of Patent:
Apr. 23, 2024

Filed:

Aug. 09, 2021

Wafer stacking structure and manufacturing method thereof

Applicants:

Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;

Jium-ming Lin, Hsinchu, TW;

Inventors:

Shou-Zen Chang, Hsinchu, TW;

Chun-Lin Lu, Hsinchu, TW;

Jium-Ming Lin, Hsinchu, TW;

Assignees:

Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;

Other;

Attorney:

JCIPRNET

Primary Examiner:

Errol V Fernandes

Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/552 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01); H01Q 1/22 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5383 (2013.01); H01L 21/4857 (2013.01); H01L 23/552 (2013.01); H01L 24/16 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01Q 1/22 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/73103 (2013.01); H01L 2224/9211 (2013.01);
Abstract

A wafer stack structure includes an interlayer, a first wafer, and a second wafer. The interlayer has a first surface and a second surface opposite to the first surface. The intermediate layer includes a dielectric material layer and a redistribution layer embedded in the dielectric material layer. The first wafer is disposed on the first surface of the interlayer. The second wafer is disposed on the second surface of the interlayer. The second wafer is electrically connected to the first wafer through the redistribution layer of the interlayer.

Find Patent Forward Citations

Chang, Shou-Zen. (2024). Wafer stacking structure and manufacturing method thereof (U.S. Patent No. 11967558). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11967558

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…