The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2024

Filed:

Apr. 24, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Khang Choong Yong, Puchong, MY;

Ying Ern Ho, Bayan Lepas, MY;

Yun Rou Lim, Bayan Lepas, MY;

Wil Choon Song, Bayan Lepas, MY;

Stephen Hall, Forest Grove, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 23/00 (2006.01); H01L 23/66 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 23/66 (2013.01); H01L 24/17 (2013.01); H05K 1/0216 (2013.01); H05K 1/025 (2013.01); H01L 2223/6627 (2013.01);
Abstract

Embodiments include package substrates and method of forming the package substrates. A package substrate includes a dielectric over a conductive layer, and a conductive line on the dielectric. The package substrate includes a plurality of conductive bumps on a surface of the conductive line, where the conductive bumps are conductively coupled to the conductive line, and a solder resist over the conductive line and the dielectric. The surface of the conductive line may be a bottom surface, where the conductive bumps are below the conductive line and conductively coupled to the bottom surface of the conductive line, and where the conductive bumps may be embedded in the dielectric. The surface of the conductive line may be a top surface, where the conductive bumps are above the conductive line and conductively coupled to the top surface of the conductive line, and wherein the conductive bumps are embedded in the solder resist.


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