The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2024

Filed:

Sep. 01, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Narasimha Lanka, Dublin, CA (US);

Kuljit Bains, Olympia, WA (US);

Lohit Yerva, Mountain View, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 11/10 (2006.01); G06F 13/16 (2006.01); G06N 20/00 (2019.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0608 (2013.01); G06F 3/0679 (2013.01); G06F 11/1004 (2013.01); G06F 13/1668 (2013.01); G06N 20/00 (2019.01);
Abstract

Systems, apparatuses and methods may provide for technology that programs a plurality of seed values into a plurality of linear feedback shift registers (LFSRs), wherein the plurality of LFSRs correspond to a data word (DWORD) and at least two of the plurality of seed values differ from one another. The technology may also train a link coupled to the plurality of LFSRs, wherein the plurality of seed values cause a parity bit associated with the DWORD to toggle while the link is being trained. In one example, the technology also automatically selects the plurality of seed values based on one or more of an expected traffic pattern on the link (e.g., after training) or a deskew constraint associated with the link.


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