The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2024

Filed:

Dec. 09, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Marcus Johannes Henricus Van Dal, Linden, BE;

Blandine Duriez, Brussels, BE;

Georgios Vellianitis, Heverlee, BE;

Gerben Doornbos, Kessel-Lo, BE;

Mauricio Manfrini, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 29/24 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10B 99/00 (2023.01);
U.S. Cl.
CPC ...
H01L 29/7869 (2013.01); H01L 21/02565 (2013.01); H01L 21/02667 (2013.01); H01L 27/1207 (2013.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 29/24 (2013.01); H01L 29/66969 (2013.01); H01L 29/78648 (2013.01); H01L 29/78696 (2013.01); H10B 99/00 (2023.02);
Abstract

A transistor includes a first gate electrode, a first capping layer, a crystalline semiconductor oxide layer, a second capping layer, a first gate dielectric layer, and source/drain contacts. The first capping layer, the crystalline semiconductor oxide layer, and the second capping layer are sequentially disposed over the first gate electrode. Sidewalls of the second capping layer are aligned with sidewalls of the crystalline semiconductor oxide layer. The first gate dielectric layer is located between the first gate electrode and the first capping layer. The source/drain contacts are disposed on the second capping layer. The crystalline semiconductor oxide layer and the source/drain contacts are located on two opposite sides of the second capping layer.


Find Patent Forward Citations

Loading…