The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2024

Filed:

Jul. 04, 2022
Applicant:

Mediatek Inc., Hsinchu, TW;

Inventors:

Tzu-Hung Lin, Zhubei, TW;

Chia-Cheng Chang, Hsinchu, TW;

I-Hsuan Peng, Hsinchu, TW;

Nai-Wei Liu, Kaohsiung, TW;

Assignee:

MEDIATEK INC., Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/043 (2006.01); H01L 23/13 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 23/043 (2013.01); H01L 23/13 (2013.01); H01L 23/3135 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 23/5383 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 23/5385 (2013.01); H01L 2224/16227 (2013.01);
Abstract

A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. Holes are formed on a surface of the substrate, wherein the holes are located within a projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material surrounds the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate are exposed by the molding material.


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