The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2024

Filed:

Sep. 07, 2021
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Liang Yi, Singapore, SG;

Zhiguo Li, Singapore, SG;

Chi Ren, Singapore, SG;

Xiaojuan Gao, Singapore, SG;

Boon Keat Toh, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11531 (2017.01); H01L 21/28 (2006.01); H01L 27/11573 (2017.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H10B 41/42 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 41/42 (2023.02); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/42328 (2013.01); H01L 29/42344 (2013.01); H01L 29/66795 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7851 (2013.01); H01L 29/7881 (2013.01); H01L 29/792 (2013.01); H10B 43/40 (2023.02);
Abstract

A semiconductor memory device includes a semiconductor substrate, a select gate on the semiconductor substrate, a control gate disposed adjacent to the select gate and having a first sidewall and a second sidewall, and a charge storage layer between the control gate and the semiconductor substrate. The control gate includes a third sidewall close to the second sidewall of the select gate, a fourth sidewall opposite to the third sidewall, and a non-planar top surface between the third sidewall and the fourth sidewall. The non-planar top surface includes a first surface region that descends from the third sidewall to the fourth sidewall. The charge storage layer extends to the second sidewall of the select gate.


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