The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2024

Filed:

Mar. 02, 2022
Applicant:

Unimicron Technology Corp., Taoyuan, TW;

Inventors:

Wen-Yu Lin, Taichung, TW;

Kai-Ming Yang, Hsinchu County, TW;

Chen-Hao Lin, Keelung, TW;

Pu-Ju Lin, Hsinchu, TW;

Cheng-Ta Ko, Taipei, TW;

Chin-Sheng Wang, Taoyuan, TW;

Guang-Hwa Ma, Hsinchu, TW;

Tzyy-Jang Tseng, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/24 (2006.01); H01L 21/56 (2006.01); H01L 23/15 (2006.01); H01L 23/31 (2006.01); H01L 23/488 (2006.01); H01L 23/544 (2006.01); H05K 1/11 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H05K 3/467 (2013.01); H05K 1/112 (2013.01); H05K 2201/0191 (2013.01);
Abstract

A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.


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