The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2024

Filed:

Jul. 29, 2021
Applicant:

Zhuhai Access Semiconductor Co., Ltd, Zhuhai, CN;

Inventors:

Xianming Chen, Zhuhai, CN;

Bingsen Xie, Zhuhai, CN;

Benxia Huang, Zhuhai, CN;

Lei Feng, Zhuhai, CN;

Wenshi Wang, Zhuhai, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 21/568 (2013.01); H01L 23/3121 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/0655 (2013.01); H01L 2224/2101 (2013.01);
Abstract

Disclosed is a manufacturing method for an embedded structure. The method includes: preparing a temporary carrier board; preparing a second circuit layer on at least one of the upper surface and the lower surface of the temporary carrier board, and preparing a first dielectric layer to cover the second circuit layer; patterning and curing the first dielectric layer to form a cavity, mounting a device in the cavity, and performing hot-curing, wherein a surface of the device provided with a terminal faces an opening of the cavity; and preparing a second dielectric layer, wherein the device is embedded in the second dielectric layer, and a surface of the second dielectric layer is higher than a surface of the terminal by a preset value.


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